Types of transfers supported by interconnection structure.

Взаимосвязь структуры определяется характером обменных операций, которые являются специфическими для каждого модуля.

The interconnection structure is determined by character of exchange operations, which are specific for each module.

Major forms of input and output for the modules:

· Memory: Typically, a memory module will consists of N words of equal length. Each word is assigned a unique numerical address (0, 1, …, N-1). A word of data can be read from or written into the memory. The nature of the operations is indicated by READor WRITE control signals. The location for the operation is specified by an address.

· I/O Module:It’s functionally similar to the memory (from internal point of view). There are two operations READand WRITE. Further, an I/O module may control more than one external device. We can refer to each of the interfaces to an external device as a port and give each a unique address (e.g., 0, 1, 2.,…, M-1). In addition, there are external data paths for the input and output of data with an external device. Finally, an I/O module may be able to send interrupt signals to the CPU.

· CPU: CPU reads in instructions and data, writes out data after processing, and uses control signals to control the overall operation of the system. It also receives interrupt signals.

· Memory to CPU: The CPU reads an instruction or unit of data from memory.

· CPU to Memory:The CPU writes a unit of data to memory.

· I/O to CPU: The CPU reads data from I/O device via an I/O module.

· CPU to I/O: The CPU sends data to the I/O device.

· I/O to or from the Memory: For these two cases, an I/O module is allowed to exchange data directly with memory, without going through the CPU, using direct memory access (DMA).

 

 

 

Multiplexer is a functional device which permits to two or more channels of data link to use the same common device of data transfer jointly.

 

		z What do buses look like? y Parallel lines on circuit boards y Ribbon (ленточный) cables y Strip (полоса) connectors on mother boards x e.g. PCI (Peripheral Component Interconnect) y Sets of wires
		Bus Structure

 

 

A system bus consists, typically, of from 50 to 100 separate lines, which can be classified into three functional groups: data, address and control lines (power lines are usually omitted ).

	Data Bus (Line) The data lines provide a path for moving data between system modules. Number of lines is referred as WIDTHof the data bus (the number of lines determines how many bits can be transferred at a time)
		z Carries data y Remember that there is no difference between “data” and “instruction” at this level! z Width of Data Bus is a key determinant of the system performance y 8, 16, 32, 64 bit

 

		Address Bus (Line)
	z Identify the source or destination of data z (e.g. CPU needs to read an instruction (data) from a given location in memory) z Address Bus width determines maximum memory capacity of the system.   z Used to address as the Main Memory, so I/O ports (the higher-order bits are used to select a particular module on the bus, and the lower-order bits select an address in the Memory or I/O port within the module). q E.g., if a width of a bus is equal to 8, then codes 01111111 and less specify cells addresses in the Main Memory module (module with 0 address), and codes from 10000000 and higher specify I/O ports which are under control of a module with an address 1.
		Control Bus(Line) Is used to control the access to and the use of the data and address lines.
	z Control and timing information(indicate validity of data and address information) y Memory read/write signal y Interrupt request

 

Command signals specify operations to be performed. Typical control lines include:

q Memory Write: Causes data on the bus to be written into the addressed location.

q Memory Read: Causes data from the addressed location to be placed on the bus.

q I/O Write: Causes data on the bus to be output to the addressed I/O port.

q I/O Read: Causes data from the addressed I/O port to be placed on the bus.

q Transfer ACK: Indicates that data have been accepted from or placed on the bus.

q Bus Request: Indicates that a module needs to gain control of the bus.

q Bus Grant: Indicates that a requesting module has been granted control of the bus.

q Interrupt request: Indicates that interrupt is pending.

q Interrupt ACK: Acknowledges that the pending interrupt has been recognized.

q Clock: Used to synchronize operations.

q Reset: Initializes all modules.

The operation of any bus is as follows:

If one of the modules “wishes” to send data to another, it must do two things:

1. Obtain the use of the bus;

2. Transfer data through the bus.

If one of the modules “wishes” to receive data from the other module it must do:

1. Obtain the use of the bus;

2. Send request to the other module, by putting the corresponding code on the address lines after formation signals on the certain control lines.

 

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer systems hierarchy.

Команда сигналы указать операции должны быть выполнены. Типичные линии управления включают в себя:

 записи в память: Причины данных по шине должны быть записаны в адрес местоположения.

 памяти Читать: Причины данные из адресной место проведения будут размещены на автобусе.

 I / O написать: Причины данных на автобусе, который будет выводиться в адрес порта ввода / вывода.

 ввода / вывода Читать: Причины данные из адресной I / O порта, который будет размещен на автобусе.

 передачи ACK: Указывает, что данные были приняты с или помещены в автобус.

 запрос шины: Указывает, что модуль должен получить контроль над автобусом.

 автобус Грант: указывает, что запрашивающий модуль был предоставлен контроль над автобусом.

 запрос на прерывание: Указывает, что прерывание находится на рассмотрении.

 Прерывание ACK: Подтверждает, что Прерывание была признана.

 часы: Используется для синхронизации операций.

 Сброс: Сброс всех модулей.

Работа любой автобус выглядит следующим образом:

Если один из модулей "пожелания", чтобы отправить данные в другую, он должен сделать две вещи:

1. Получить использования автобусов;

2. Передача данных по шине.

Если один из модулей "пожелания", чтобы получить данные из другого модуля он должен делать:

1. Получить использования автобусов;

2. Отправить запрос на другой модуль, поместив соответствующий код на адресные линии после формирования сигналов на некоторых линиях управления.

 

Компьютерные системы содержат ряд различных шин, которые обеспечивают пути между компонентами на различных уровнях иерархии компьютерных систем.